I am an Assistant Teaching Professor in the Department of Electrical and Computer Engineering at Worcester
Polytechnic Institute (WPI), where I teach topics in computer engineering. I discovered my passion for teaching as a graduate teaching assistant at WPI, where I received my Ph.D. in Electrical and Computer Engineering after completing B.S. and M.S. degrees in the same subject. My research in microarchitectural security, FPGA-CPU systems, and cloud system security has been published in peer-reviewed security journals and a book chapter.
Research Interests
- Side-channel attacks
- Speculative execution attacks
- Virtual machine and cloud system security
- FPGAs and FPGA-CPU coprocessing platforms
- Hardware and firmware defenses against microarchitectural vulnerabilities
Publications
- T. Tiemann, Z. Weissman, T. Eisenbarth, and B. Sunar, "Microarchitectural Vulnerabilities Introduced, Exploited, and Accelerated by Heterogeneous FPGA-CPU Platforms" , in Security of FPGA-Accelerated Cloud Computing Environments, edited by J. Szefer and R. Tessier, New York City: Springer (forthcoming).
- Z. Weissman, T. Tiemann, T. Eisenbarth, and B. Sunar, Microarchitectural Security of AWS Firecracker VMM for Serverless Cloud Platforms, under review.
- T. Tiemann, Z. Weissman, T. Eisenbarth, and B. Sunar, IOTLB-SC: An Accelerator-Independent Leakage Source in Modern Cloud Systems, AsiaCCS 2023 (forthcoming). [arXiv] [PDF] [BibTeX]
- Z. Weissman, T. Tiemann, D. Moghimi, E. Custodio, T. Eisenbarth, and B. Sunar, JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms, IACR Transactions in Cryptographic Hardware and Embedded Systems, Volume 2020, Issue 3. [arXiv] [PDF] [poster] [BibTeX] [ZDNET] [Tom's Hardware]